1. Field of the Invention
The present invention relates to controllers for switching power supplies and to methods for protecting power switches thereof. More particularly, this invention pertains to a primary side control module for a switching power supply with pulse width modulation for controlling the switching of a power FET and to a method for protecting the FET against burnout.
2. Description of the Prior Art
If there is any one component that is absolutely vital to the operation of a computer, it is the regulated power supply. The supply converts the a.c. of a home or office line to the d.c. required to operate the computer and its components and peripherals.
Switched- or switch mode power supplies (“SPMS”) are often employed rather than linear power supplies (“PSU”) despite greater complexity when reduced size and greater operational efficiency are desired. In an SPMS, a switching regulator switches a load current off and on rapidly to stabilize the output voltage rather than the linear regulator of a PSU.
An SPMS operates by switching a power FET to regulate the current. The switched current passes through an inductor or the primary of a transformer. When the current flows through the inductor or primary, energy is stored for ultimate transfer as d.c. to the output when the current is switched off. This assures a steady d.c. output.
Standard integrated circuits or chips exist for controlling current switching of the power FET in an SPMS. One well recognized family of chips consists of the fixed frequency current mode pulse width controller having the designation UC 3842. Such chip is commercially available from numerous sources including, but not limited to, Fairchild Semiconductor Corporation of South Portland, Me. and Phillips Semiconductors of Eindhoven, The Netherlands.
Switching power supplies of the above-described type, in which a fixed frequency current mode pulse controller provides a signal that controls the “OFF” and “ON” cycling of a power MOSFET can experience a catastrophic failure mode and burnout due to failure of the switching mode. FIGS. 1(a) through 1(e) are a series of waveforms that illustrate the nature of the above-described failure mode.
It is known that a controller such as a UC 3842 generates a PWM waveform output through the interaction of a sawtooth waveform with a d.c. voltage level Vint, comprising the output of an error amplifier (internal to the controller). The waveform, comprising a series of voltage ramps, is generated in accordance with signals input to the controller from external circuitry. The interaction of a sawtooth waveform, shown in FIG. 1(a), with Vint during “normal” conditions is illustrated by FIGS. 1(b) and 1(c).
Viewing FIGS. 1(b) and 1(c) together, one can see that the leading edge of an output pulse 10 is generated by the concurrence of the value of a voltage ramp 12 of the sawtooth waveform with the output of the internal error amplifier of the controller while the trailing edge of the pulse is concurrent with the resetting edge 14 of the voltage ramp. As long as Vint remains within the bounds of the voltage ramp, a stream of PWM pulses will be generated within the controller and subsequently output to the gate of the power MOSFET of the power supply.
A problem occurs when the error amplifier output Vint ranges below the bounds of the voltage ramp. (Note: Should Vint go above the peak of the ramp, a critical condition does not occur. Rather, the power supply will cease to function as no signal will be received for gating the power MOSFET.) Such problem is illustrated in FIGS. 1(d) and 1(e). As shown in FIG. 1(d), a voltage drop 16 lowers the value of Vint beneath the lower bound of the sawtooth waveform 18. This is reflected in the resultant waveform output from the controller as illustrated in FIG. 1(e). As can be seen, a first pulse 20 is formed as above. That is, the intersection of the ramp 12 with Vint creates a the leading edge of the pulse 20 while the trailing edge of the pulse 20 occurs with the subsequent resetting of the voltage ramp. Thereafter, a leading edge 22 is formed by the intersection of the downgoing portion 16 of Vint with the next voltage ramp 24. However, a trailing edge of the inchoate “pulse” is never formed since, as Vint now lies below the lower bound of the sawtooth waveform 18, there no longer occurs a coincidence of the error amplifier output Vint with a resetting edge of the voltage ramp 24 or, for that matter, with the resetting edge of any subsequent voltage ramp of the sawtooth waveform 18. Thus, rather than forming a second completed pulse, the output of the controller simply goes “HIGH”, causing the voltage at the gate of the driven MOSFET to a continuous conduction mode that produces the failure mode discussed above.